micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com M2004-02 preliminary specifications 1 micro netw orks an integrated circuit systems compan y iso 9001 registered iso 9001 registered M2004-02 frequency synthesizer description the M2004-02 integrates a high performance phase locked loop (pll) with a voltage controlled saw oscillator (vcso) to provide a low jitter frequency synthesizer in a 9mm x 9mm surface mount package. the internal high ??saw filter provides low jitter signal performance and determines the maximum output frequency of the vcso. a programmable output divider can divide the vcso frequency to achieve an output as low as 38.88mhz. the input to the frequency synthesizer is provided by selecting between a differential input clock or a single ended input clock. the output frequency is an integer multiple of the input reference frequency. the multiplying factor is programmed via a 6 bit parallel address. an external loop filter sets the pll bandwidth which can be optimized to provide jitter attenuation of the input reference clock. the bandwidth control, low phase noise, and hold features make the M2004-02 ideal for use as a clock jitter attenuator, frequency translator, and clock frequency generator in oc-3 through oc-192 applications. output clock frequency up to 700mhz internal low-jitter saw-based oscillator intrinsic jitter <1ps rms (12khz - 20mhz) differential input compatible with lvpecl, l vds, hstl, sstl, etc. dual input mux parallel programming t unable loop filter response differential lvpecl outputs 3.3v operation small 9mm x 9mm smt package features applications sonet / sdh / 10gbe system synchronization add / drop muxes, access and edge switches line card system clock cleaner / t ranslator optical module clock cleaner / translator
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com M2004-02 preliminary specifications 2 micro netw orks an integrated circuit systems compan y nf out f out parallel programming interface m5:m0 mux ref_clk dif_ref 0 ndif_ref 0 mr op_out nop_out op_in nop_in +m vc nvc vcso ref_sel n1 phase detector & active loop filter output divider functional description: the internal pll will adjust the vcso output frequency to be m (feedback divider) times the selected input reference clock frequency. note that the product of m x the input reference frequency must be such that it falls within the lock range of the vcso. the n output divider can be programmed to divide the vcso output frequency by 1, 2, 4, or 8 and provide a 50% output duty cycle. the multiplying factor is programmed via a 6-bit parallel bus. the relationship between the vcso frequency, the m divider, and the differential input reference clock is defined as follows: f vcso = f ref_clk x m when the n output divider is included, the complete relationship for the output frequency is defined as: fout = f vcso = f ref_clk x m n n the n1 input can be hard wired to set the n divider to a specific state that will automatically occur during power-up. functional block diagram
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com M2004-02 preliminary specifications 3 micro netw orks an integrated circuit systems compan y functional description loop filter figure 2 table 1. recommended loop filter values the M2004-02 requires the use of an external loop filter via the provided filter pins. due to the differential design, the implementation requires two identical rc filters as shown in figure 2. ref_clk vcso m n fout rloop cloop rpost cpost frequency frequency 19.44mhz 622.0800mhz 32 1 622.0800mhz 5k ? 1mf 20k ? 250pf vc nvc op_out nop_out op_in nop_in rloop rloop cloop cloop rpost rpost cpost cpost
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com M2004-02 preliminary specifications 4 micro netw orks an integrated circuit systems compan y pin descriptions table 2 pin number name i/o configuration description 1, 2, 3 gnd gnd power supply ground 4, 9 op_in, nop_in analog i/o used for external loop filter. see figure 2. 5, 8 nop_out, op_out analog i/o used for external loop filter. see figure 2 6, 7 nvc, vc input vcso differential control voltage input pair 10, 14, 26 gnd gnd power supply ground 11, 19, 33 v cc po wer positive supply pins 12, 13 n0, n1 input pull - down determines the output divider value as defined in table 3c. lvcmos / lvttl interface levels. 15, 16 fout, nfout output unterminated differential output, 3.3v lvpecl levels. 17 mr input pull - down logic high resets the reference frequency and n output dividers. logic low enables the outputs. l vcmos / lvttl interface levels. 18, 20, 21 nc no connection 22 ref_sel input pull - down selects between the different reference clock inputs as the pll reference source. see table 3d. l vcmos / lvttl interface levels. 23 ndif_ref input pull - down inverting differential clock input. compatible logic levels include lvcmos, lvds, hstl, etc. 24 dif_ref input pull - down non-inverting differential clock input. compatible logic levels include lvcmos, lvds, hstl, etc. 25 ref_ clk input pull - down input reference clock. lvcmos / lvttl interface levels. 27, 28, 29, 30, 31 m0, m1, m2, m3, m4 input pull - down m divider inputs. data is always transparent. no latch signal is required. 32 m5 input pull - down 34, 35, 36 dnc do not connect. internal test pins.
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com M2004-02 preliminary specifications 5 micro netw orks an integrated circuit systems compan y table 4 pin characteristics symbol parameter test conditions min typical max units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? table 5b programmable vcso frequency function vcso frequency 32 16 8421 (mhz) m divide m5 m4 m3 m2 m1 m0 325 13 001101 350 14 001110 375 15 001111 400 16 0 1 0 0 0 0 600 24 011000 625 25 011001 650 26 011010 note 1: these m divide values and the resulting frequencies correspond to a reference frequency of 25mhz. table 5a parallel & serial modes function inputs mr m n conditions hx x reset, forces outputs low. ld at ad at ad a ta on m and n inputs passed directly to the m divider and n output divider. note: l = low; h = high; x = don? care; = rising edge transition; = falling edge transition
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com M2004-02 preliminary specifications 6 micro netw orks an integrated circuit systems compan y table 5c parallel mode function serial mode function table 5d inputs n divider output frequency (mhz) n1 n0 value min max 00 1 311 700 01 2 155.5 350 10 4 77.75 175 11 83 8.875 87.5 inputs ref sel reference 0 diff_ref 1 ref_clk power supply dc characteristics symbol parameter t est conditions min typ max units v dd po wer supply voltage 3.135 3.3 3.465 v i dd po wer supply current 162 ma v cc = 3.3v 5%, t a = 0 c to 70 c l vcmos/lvttl dc characteristics symbol parameter test conditions min max units v ih input high ref_sel, ref_clk, 2 vcc + 0.3 v v oltage n0:n1, m0:m5, mr v il input low ref_sel, n0:n1, m0:m5, mr v oltage ref_clk -0.3 1.3 v i ih input high m5 v dd = v in = 3.465v 5 a current n0, n1, mr, m0:m4, s_clock, v dd = v in = 3.465v 150 a ref_sel, ref_clk i il input low m5 v dd = 3.465, v in = 0v -150 a current n0, n1, mr, m0:m4, v dd = 3.465, v in = 0v -5 a ref_sel, ref_clk differential input dc characteristics symbol parameter test conditions min max units i ih input high ndif_ref 5 a current dif_ref 150 a i il input low ndif_ref -150 a current dif_ref -5 a v p-p p eak to peak input voltage 0.15 v v cmr ref_sel, ref_clk v cc +0.3 v cc -0.85 v v cc = 3.3v 5%, t a = 0 c to 70 c
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com M2004-02 preliminary specifications 7 micro netw orks an integrated circuit systems compan y input frequency characteristics l vpecl dc characteristics symbol parameter signal min max units v oh output high voltage: note 1 fout, nfout v dd e 1.4 vcc e 1.0 v v ol output low voltage: note 1 fout, nfout v dd e 2.0 vcc e 1.7 v v swing p eak-to-peak output voltage swing fout, nfout 0.6 0.85 v note 1: output terminated with 50 1 to v dd e2.v symbol parameter test conditions min max units f in input frequency dif_ref 10 175 mhz ndif_ref 10 175 mhz v cc = 3.3v 5%, t a = 0 c to 70 c ac characteristics symbol parameter test conditions min typ max units f out output frequency 38.88 667 mhz noise single side band 1khz offset -72 dbc/hz phase noise 10khz offset -94 dbc/hz 100khz offset -123 dbc/hz j (t) jitter (rms) 12khz to 20 mhz 0.69 ps odc output duty cycle 50 % t r output rise time fout = 155mhz 20% to 80%, each 350 450 550 ps (note 1) for output pairs fout = 311mhz output of pair measured 325 425 500 ps fout0, nfout0 & fout= 622mhz is terminated into 50 1 200 275 350 ps fout1, nfout1 load biased at vcc-2v t f output fall time fout = 155mhz 20% to 80%, each 350 450 550 ps (note 1) for output pairs fout = 311mhz output of pair measured 325 425 500 ps fout0, nfout0 & fout = 622mhz is terminated into 50 1 200 275 350 ps fout1, nfout1 load biased at vcc-2v t lock pll lock time 1 ms note: the output frequencies of 155mhz, 311mhz and 622mhz were chosen for device characterization as these are common optical n etwork clock frequencies.
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com M2004-02 preliminary specifications 8 micro netw orks an integrated circuit systems compan y parameter measurement information odc & t period pulse width t period t pw t period odc = clock inputs and outputs 20% 80% 80% 20% t r t f v swing input and output rise and fall time
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com M2004-02 preliminary specifications 9 micro netw orks an integrated circuit systems compan y test evaluation board j3 9-pin d connector pin signal 1mr 3 s_clock 5 s_data 7 s_load 9 np_load sw1 1 2345678 p osition ref select m5 m4 m3 m2 m1 m0 n/c off ref_clk0 ? ? ? ? ? ? n/c on ref_clk1 ? ? ? ? ? ? n/c jp1: n0 logic ? when installed jp2: n1 logic ? when installed
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.c 2 M2004-02 preliminary specifications micro netw orks an integrated circuit systems compan y mechanical dimensions & pin configuration pin# designation 1 gnd 2 gnd 3 gnd 4 op_in 5 nop_out 6 nvc 7vc 8 op_out 9 nop_in 10 gnd 11 vcc 12 no 13 n1 14 gnd 15 fout 16 nfout 17 mr pin# designation 18 n/c 19 vcc 20 n/c 21 n/c 22 ref_sel 23 ndif_ref 24 dif_ref 25 ref_clk 26 gnd 27 m0 28 m1 29 m2 30 m3 31 m4 32 m5 33 vcc 34, 35, 36 dnc ordering information dimensions are in inches, (dimensions) are in mm. part number M2004-02-622.0800 series model vcso center frequency (i.e. 622.0800mhz) a vailable vcso frequencies 500.0000 666.5143 693.4830 micro networks an integrated circuit systems company 324 clark street worcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 european sales headquarters hertogsingel 20 6214 ad maastricht t he netherlands tel: +31-43-32-70912 fax: +31-43-32-70715 www.micronetworks.com rev. 7.3 micro networks makes no assertion or warranty that the circuitry and the uses thereof disclosed herein are non-infringing on any valid us or foreign patents. micro networks assumes no liability as a result of the use of said specifications and reserves the right to make changes to specifications without notice. contact your nearest micro networks sales representative office for the latest specifications. o rientati o n ta b [] .354 [ 9.0 ] .200 [ 5.1 ] r .006 [r 0.2 ] .025 [ 0.6 ] pin #1 c # 36 l .041 [ 1.0 ] .007 [ 0.2 ] c c l l #1 0 .354 [ 9.0 ] #2 8 #27 #1 9 #1 8 .110 [ 2.8 ] 622.0800 669.1281 625.0000 669.3266 627.3296 672.1600 644.5313 690.5692
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